Conventional integrated circuits (ICs) are often designed to minimize dynamic power consumption and leakage. Leakage (static power consumption) is the power dissipated due to sub-threshold leakage and current flow through a reverse-biased p-n junction between diffusion and substrate. Leakage accounts for the majority of power dissipated when a standard cell in an integrated circuit is inactive, an important metric to measure and optimize for battery-powered applications.
Leakage in a standard cell in an IC increases as the size of the components in the cell decreases and as the thickness of the gate insulating layer of the transistors in the cell decreases. At smaller process geometries, leakage begins to dominate the power consumed by CMOS devices. In order to control both dynamic (switching) power consumption and leakage, engineers can employ various power management techniques.
One technique to reduce power consumption involves utilizing multi-voltage transistors, in which transistors with different switching thresholds are employed in different regions of the IC or chip. A second technique to reduce power consumption involves the use of power shut-off (PSO), which refers to completely powering down a chip's functional block (or group of standard cells receiving the same voltage from a common source) when it is not in use. This has been implemented in different blocks as hard macros or voltage islands.
Presently, in most IC design tools, a power grid is designed prior to standard cell placement. Specifically, a power grid comprising a global grid and a local grid are routed on a chip. The global grid comprises, in most chips, upper level metal layers that are used for global power distribution, usually having a thickness greater than that of the metal layers in the local grid. The local grid comprises, in most chips, lower level metal layers that serve as local interconnects (straps) between standard cell rails and the global grid. The standard cell rails may be considered part of the local grid. The local grid, in some embodiments, forms a block of approximately 5-100 microns per side.
The place and route process in such designs is based on standard cell placement and abutment, with shared power and ground rails. However, when different power nets (e.g., grids) are required for different standard cells, these fundamental assumptions can no longer apply. Thus, design workarounds are created and/or utilized. However, to date, such workarounds have had limitations.
One workaround involves voltage areas. A “voltage area” is generally a region of an integrated circuit layout in which the power supply rails of all standard cells in the region are coupled to a single power net. The cells in a voltage area can be coupled to one of a plurality of power nets, in which each power net is configured to operate at one of a plurality of different power-down states. In some chips, different voltage areas belonging to the same power domain are located in a variety of locations on the chip. Thus, a first voltage area belonging to a first power domain may be located on a side of the chip opposite from that of a second voltage area also belonging to the first power domain. Standard cells grouped in such voltage areas can be placed in non-ideal chip locations (e.g., locations not optimized for timing and routing). This leads to sub-par placement quality. To optimize certain parts of the design for timing, cells coupled to different power nets can be placed in nested voltage areas. In such instances, some nested voltage areas have hard macros with pins belonging to different power domains, resulting in uncommon voltage area patterns. Such irregular patterns create floor planning complications, such as signal timing issues and layout congestion. Thus, conventional implementation tools have problems or are impractical for implementing such designs.
Another design around utilizes dual rail cells (DRCs), having one pin that can receive a voltage from a common power supply rail, and a second pin (e.g., in the middle of the cell) configured to receive a voltage for “always on” (AON) cells (e.g., buffers) and clock isolation (ISO) cells. Certain DRCs also require a voltage to be applied at the first and second pins (e.g., dual rail flip-flops).
In the DRC methodology, a second power grid is routed to provide a common voltage to a plurality of DRCs. However, the routing resource requirements for such an approach can be significant, as in the case when all of the flip-flops in a design are DRCs. Additionally, the routing signal quality may be compromised. In addition, routing may be continuously altered during design optimization. Thus, significant work may be required to ensure that the second power grid is correctly routed prior to tapeout.
During synthesis of AON cells, cross-domain signals (e.g., signals from one AON voltage area to another AON voltage area across a domain that is typically off) may be a common occurrence. There may also be cases where a signal from one voltage area to another voltage area could be most effectively routed through an AON voltage area. This leads to design rule check violations. AON synthesis also generally attempts to utilize designated AON buffers, which can lead to inefficient circuit design.
A further technique to reduce power consumption involves a multi-supply, multi-voltage (MSMV) approach, which entails dividing a chip into areas (e.g., “power domains”) supplied with different on/off states and/or different voltages, and then assigning the various functional blocks or standard cells forming the design to the different power domains. A power domain differs from a voltage area, in that power domains specify power intent (e.g., power-on or power-down states). In contrast, a voltage area is a region in which all of the standard cells have power rails coupled to a single power net. Typically, a power domain can consist of one or more corresponding voltage areas. In the MSMV technique, the power grid for each voltage area is laid out, and cells requiring a particular voltage are placed so that they can be connected to a desired power rail or strap in the grid. (Herein, a “rail” generally refers to a metal line or other physical structure on the IC that provides a relatively stable, predetermined voltage in a region of the IC. A “strap” generally refers to a relatively long, often straight power bus routed in one or more metal layers that connect between a rail and a global grid.)
Specifically, in a MSMV approach, power domains are specified by the voltages at which various circuitries operate. For example, some domains may be coupled to a first, relatively high voltage, some domains may be coupled to a second, relatively low voltage, and optionally, some domains may be coupled to a third voltage different from the first and second voltages. Domains operating at the same voltage generally have different on/off states or power-down cycles. Cells that receive the same supply voltage and that have the same power-on and power-down states may be considered to be in a “voltage area.” The different voltage areas can be large or small, but in one design approach, they tend to be large in order to reduce the grid complexity for the chip.
For example, FIG. 1 shows a region 100 of an IC comprising a first voltage area 110 and a second voltage area 120. First voltage area 110 includes cells 101, 103, 105, 107, and 109, and second voltage area 120 includes cells 111, 113, 115, 117, and 119. Each of the plurality of cells in voltage area 110 comprises a first pin (e.g., pin 102 in cell 101) configured to receive a ground potential (e.g., a potential of about zero volts) from power strap (strap) 150 via power rail 152. Strap 150 is configured to receive a ground potential from an external ground source (not shown) during an operational state (e.g., an ON state) of the circuitry in voltage area 110. Additionally, each of the plurality of cells in the first voltage area 110 includes a second pin (e.g., pin 104 in cell 101) configured to receive a first voltage (e.g., a predetermined or reference voltage) via power rail 142 from power strap 140. Strap 140 receives the first voltage from an external voltage source (not shown). Thus, during the operational state, each cell in the first voltage area 110 receives the first voltage and is coupled to the ground potential.
Similarly, each of the plurality of cells in the second voltage area 120 comprises a first pin (e.g., pin 112 in cell 111) configured to receive the ground potential from strap 150 via power rail 154. As discussed above, strap 150 is configured to provide a ground potential during an operational state of the second voltage area 120. Additionally, each of the plurality of cells in the second voltage area 120 includes a second pin (e.g., pin 114 in cell 111) configured to receive a second voltage (e.g., a predetermined or reference voltage) via power rail 162 from power strap 160. The first and second pins (e.g., pin 102 and pin 104 in cell 101) are static rail pins (SRPs). Standard cells having SRPs are generally placed adjacent to each other, and the SRPs are connected to a common power grid in the same domain or voltage area. Strap 160 receives the second voltage from an external voltage source (not shown). Thus, during the operational state, each cell in the second voltage area 120 receives the second voltage and is coupled to the ground potential. Furthermore, during the operational state, each of the cells in the second voltage area 120 may operate at a voltage different from that of the cells in the first voltage area 110.
By utilizing different voltage areas, the voltage provided to the first voltage area 110 (i.e., cells 101-109 in FIG. 1) can remain in the operating mode (e.g., an “ON” state), while the voltage provided to the second voltage area 120 (i.e., cells 111-119 in FIG. 1) can be switched off when the circuitry in the second voltage area 120 is in a non-operational state (e.g., an “OFF” state). Doing so reduces the power consumed by the second voltage area 120 of IC 100, thus minimizing the dynamic power consumption. By configuring first and second voltage areas 110 and 120 to operate at different voltages, the static and dynamic power consumption in the IC can be reduced or minimized.
However, one problem associated with voltage area-based designs (e.g., the design of FIG. 1 having first and second regions 110 and 120) is that such designs utilize power straps 140 and 160 and power rails 142 and 162 that can inhibit cell placement. That is, with conventional circuits like those in area 100, only those cells operating at the first voltage can be grouped in the first region 110 of FIG. 1, while those cells operating at the second voltage must be grouped in a different region (e.g., the second region 120 of FIG. 1). Thus, cells cannot be freely placed, and in some instances, such designs require repeated changing of the RTL code during circuit design to put cells into particular hierarchies that belong to a particular power domain or voltage area. However, instead of creating a large number of voltage areas (e.g., greater than 10), cell modules belonging to the same power domain were grouped together and placed adjacent to a limited number of voltage areas. Power grids were then drawn accordingly. However, doing so increased design costs and reduced design efficiency.
Additionally, voltage area- or region-based layout designs can inhibit or impede designing for ideal or optimal timing conditions. For example, referring to FIG. 1, cell 101 may be designed to communicate with cell 119 (e.g., via data connections not shown in FIG. 1). Ideally, for optimal timing, cell 101 would be placed adjacent to cell 119. However, due to each cell's respective voltage requirement, cell 101 is placed in first region 110, and cell 119 is placed in second region 120. Thus, the distance between the two cells can cause significant timing issues (e.g., a time delay) when the cells belong to different voltage regions. As a result, regional layout designs can limit cell placement and inhibit or impede compliance with timing constraints.
Additionally, the MSMV technique and the PSO technique require the insertion, placement, and connection of specialized power management structures, such as level shifters, power pads, switch cells, isolation cells, and state-retention cells. Furthermore, some inter-voltage area (VA-VA) buffering designs can be problematic. For example, design optimization tends to add buffers with a hierarchy defined for one voltage area, but such buffers cannot be placed outside that particular voltage area. For more detailed designs, voltage area designs create floorplan and implementation problems. Although techniques such as MSMV design can reduce static and dynamic power consumption, such techniques increase the complexity associated with design, verification, and implementation tools and methodologies. For example, MSMV techniques can lead to significant increases in tapeout schedule, tool runtime, timing closure, ECO checking, multi-voltage rule checking, and design rule check (DRC)/layout versus schematic (LVS) debugging. Furthermore, while using a single technique (e.g., MSMV) in isolation may be relatively simple, often a combination of these techniques (e.g., MSMV and PSO) is used to meet certain power targets. Using multiple techniques concurrently increases the complexity of the development flow.
This “Background” section is provided for background information only. The statements in this “Background” are not an admission that the subject matter disclosed in this “Background” section constitutes prior art to the present disclosure, and no part of this “Background” section may be used as an admission that any part of this application, including this “Background” section, constitutes prior art to the present disclosure.